In modern computer system design it is common for multiple devices to be coupled to a common communication bus. Moreover, it is also common for more than one of these devices to possess the capability to act as a bus master which controls the transfer of data, control and address signals between itself and another device over the common communication bus. In such computer systems it is therefore necessary to implement an arbitration scheme to determine the order in which these multiple bus master devices may control the common bus. The arbitration scheme is utilized during situations in which two or more of the bus master devices simultaneously seek to control the common bus.
The arbitration scheme may be viewed as a component of the bus protocol. The bus protocol is a complex set of pre-defined rules which govern the use of the common communication bus. Generally, a bus protocol can be viewed as a set of rules which allow different devices to communicate over a common bus without interfering with one another. In a multiple bus master system it is necessary to ensure that each device that attaches to the common communication bus, obeys the arbitration scheme of the common bus, so as to enable each of these devices to individually access or control the common bus devices and to prevent contention therebetween. In most computer system designs, bus master devices having a common arbitration scheme which is identical to, or at least compatible with the arbitration scheme defined by the protocol of the common communication bus are utilized. However, in certain instances, it is necessary to utilize a particular bus master device which is not readily available with the arbitration control scheme used to access the common bus. In such instances, the designer may be forced to undertake a costly customization to design a version of the required bus master having the desired arbitration scheme. The cost effective alternative to such a design effort would be to use a separate arbiter device to perform an arbitration protocol conversion, thereby efficiently rendering the requisite bus master device compatible with the common communication bus arbitration protocol. In this manner a designer may implement a computer system design using "off-the-shelf" components, thereby facilitating expeditious design and reducing the cost associated with the system.
Arbitration schemes for controlling a common communication bus may be broadly classified as either distributed arbitration schemes in which arbitration devices (or arbiters) associated with the bus master devices all participate in the arbitration operation, or centralized (i.e. single-point) arbitration schemes in which a single centralized arbiter is active to allocate access and control of the common communication bus among conflicting bus master devices requesting such access and/or control.
In distributed arbitration schemes, each of the multiple bus master devices is typically assigned a priority which reflects the sequence in which each of the multiple bus master devices may control the bus. A bus master device having a high priority will take precedence over a bus master device having a low priority when each of the devices simultaneously requests control of the common bus. Priority may be determined by the position at which a particular bus master device attaches to the common bus. In the distributed arbitration scheme described in U.S. Pat. No. 5,408,129 to Farmwald et al. (issued Apr. 18, 1995), each device on the bus is assigned a unique device ID number. When a collision between bushmaster requests to control the common bus occurs, each bus master device seeking to control the bus drives a single BusData line during a single bus cycle corresponding to its assigned master ID number, and a fixed priority scheme is implemented to sequence the requests in a bus arbitration queue maintained by at least one device. Further bus master requests are disabled until the queue is cleared.
Distributed arbitration designs are not the optimum means for performing bus arbitration in every system utilizing a commonly accessed bus. Typically the distributed arbitration design is inflexible and it is difficult to affect a modification in priority assignments. Moreover, priority assignments may lead to the "starvation" of a lower priority device. Consequently, such prioritization schemes mandate a classification of the operations to be performed by each of the bus masters, to ensure that low priority devices, which control the bus less frequently than high priority devices, are not responsible for performing the most important operations over the common data bus. Furthermore, in priority schemes such as the scheme disclosed in the patent to Farmwald et al., bus cycles are devoted to the resolution of conflicting bus master requests thereby reducing the bandwidth of the common bus. Finally, depending upon the distributed arbitration scheme that is implemented, the number of bus master devices that may be arbitrated thereby may be limited.
Accordingly, certain designs for systems implementing a commonly accessed bus system dictate the implementation of the aforementioned single point arbitration scheme. Systems including a commonly accessed bus in which the arbitration is centrally performed by a single arbitration control circuit often include a separate arbitration device associated with each bus master device. In such systems, one of these arbitration devices is typically activated to provide the centralized arbitration operation, while the other arbiters serve as slave arbiters thereto. For example, U.S. Pat. No. 5,377,331 entitled "Converting A Central Arbiter To A Slave Arbiter For Interconnected Systems" issued Dec. 27, 1994 to Drerup et al. and assigned to International Business Machines Corporation (hereinafter "IBM", IBM is the assignee of the present application as well) teaches a system which enables the connection of plural subsystems each comprising a local bus arbiter for arbitrating device requests for devices within the subsystems, to a common Micro Channel bus (Micro Channel is a trademark of IBM Corporation) by providing conversion logic devices which effectively transform the local arbiters on the corresponding subsystems into slave arbiters. In the patent, the single subsystem (illustratively termed the host system) which is responsible for arbitrating the common bus is not provided with a conversion logic device. The conversion logic includes two requesting arbiters, one of which arbitrates control of the internal subsystem bus and the other, which arbitrates for control of the common Micro Channel bus. Once a conversion logic device obtains control of the common Micro Channel bus, it relinquishes control of the internal subsystem bus, and an arbitration cycle is initiated, after which the subsystem device with the highest priority obtains control of the internal subsystem bus and is capable of passing commands and/or data through the conversion logic device to other devices in other subsystems coupled to the common Micro Channel bus. Since Drerup et al. require arbitration of the common Micro Channel bus, it follows that the bandwidth of that common bus is reduced. Additionally, as a result of the successive stages of arbitration that characterize the Drerup et al. invention, extra arbitration cycles are required for access to the common Micro Channel bus. However, Drerup et al. do teach an implementation of centralized arbitration by separate bus master devices each including an arbiter circuit.
In other single point or centralized bus arbitration systems, the activated arbiter logic is enabled via an activation signal on an arbitration bus. Such systems are typically implemented by providing additional I/O on each of the arbitration devices associated with each bus master device. The additional I/O serves to enable an arbitration control circuit associated with a single bus master device, while disabling each of the arbitration control circuits on the other bus master devices. However, such an implementation adds I/O to each of the arbitration devices, thereby rendering the arbitration bus more complex and costly.
It is therefore desirable to provide a means for providing centralized bus arbitration while providing protocol conversion logic which solves the aforementioned design problems associated with incompatible bus master devices. Furthermore, it is desirable to provide such a solution which does not require additional I/O or arbitration cycles, and is inexpensive, simple to implement and flexible so as to promote the design of lower cost computing systems.